Building Bootloader for Altera® SoC FPGAs - 31 Minutes In this class, you will learn how to develop and build the flows supported to generate all the files necessary for the booting stages for Altera® SoC FPGAs. With an example of Agilex™ SoC FPGA build flow using the Golden System Reference Design from GitHub repository you will be able to understand how to generate the first and second-stage bootloaders. Course Objectives At course completion, you will be able to: Understand the booting stages and tools to build the first and second-stage bootloaders. Identify the boot flows and sources to generate files for a single image booting. Identify the sources to retrieve and build the bootloaders and the boot stages. How to build using the tools to build the necessary files for building a bootloader, and how the files generated from the project in Quartus Software compilation are part of the software flow. Command line tools and definitions for working to generate your bootloader files for your design. Skills Required Altera® SoC FPGAs architecture and hard processor knowledge. Software and hardware project build flows. Embedded systems Suggested previous e-learnings: - Getting Started with Linux OS for Altera® SoC FPGAs - Agilex™ 5 SoC FPGAs Software Flow - Agilex™ 5 HPS Overview If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com. Reference Course Code: FPGA_OSOCSSBL. FPGA_OSOCSSBL. <p>Building Bootloader for Altera SoC FPGAs</p>