External Memory Interfaces in Agilex™ FPGAs (Part 1): Introduction - Same Course in Simplified Chinese: Altera® Agilex®器件中的存储器接口介绍 Same Course in Japanese: インテル Agilex™ デバイスのメモリー・インターフェイスの概要 60 Minutes This training is part 1 of 4. The Altera® Agilex™ family of FPGAs introduce brand new, higher performance architectures for implementing external memory interfaces, including DDR5 running at up to 5.6 Gbps on some devices. This first part of the training introduces the memory options available and describes how the architecture of these devices makes such performance possible. It also describes the unique features of the built-in hard memory controller needed to achieve such speeds. Course Objectives At course completion, you will be able to: Know the external memory interface (EMIF) options available in Agilex™ FPGAs Understand the new architectural features for implementing memory interfaces Learn about the features of the Hard Memory Controller that make higher speed interfaces possible Skills Required Background in digital logic design Basic knowledge of memory interfaces and their implementation in Altera® FPGA devices Familiarity with the Quartus® Prime software If the audio for the course does not start automatically, press pause and then play on the course player. A transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OAGMEM101. FPGA_OAGMEM101. <p>External Memory Interfaces in Agilex FPGAs (Part 1): Introduction</p>