Introduction to High-Level Synthesis (Part 1 of 7) - 65 Minutes In the class, you will learn how to use the Altera® HLS Compiler to synthesize and verify IP components for Altera® FPGAs. We will first discuss the benefits of HLS then talk about features of the Altera® HLS Compiler. You will learn how to use the Altera® HLS compiler to perform emulation functional debug, co-simulation with a behavioral simulator and finally integrate the generated IP within an Altera® Quartus® software project. Course Objectives At course completion, you will be able to: Use the Altera® HLS compiler to synthesize a Component compatible with the Altera® Quartus Prime software design flow Co-simulate your HLS Component using an RTL simulator with a software testbench Integrate the HLS Component within an FPGA design Skills Required Basic understanding of the C++ programming language Basic understanding of FPGAs and the Altera® Quartus Prime Software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OHLS1. FPGA_OHLS1. <p>Introduction to High-Level Synthesis (Part 1 of 7)</p>