FPGA JTAG Circuit for Cyclone II - FPGA JTAG Circuit for Cyclone II Hi. I am developing a Cyclone II - EP2C20AF256I8N FPGA schematic using the EPCS16SI8N memory. I wanted to know if the following schematic is correct to program it through USB BLASTER ALTERA CPLD. If I have any mistake, could you please correct me? Is it necessary to put the two headers to record it also by AS? Replies: Re: FPGA JTAG Circuit for Cyclone II Thank you FvM for sharing the solution. I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Replies: Re: FPGA JTAG Circuit for Cyclone II Hello, the configuration interface is implemented correctly. You don't need a second AS header, flash will be programmed through JTAG by using JTAG indirect configuration.