Error (Suppressible): ../../ip/ed_sim/ed_sim_tester_0/sim/ed_sim_tester_0.vhd(93): (vopt-1130) port "channel_strobe_out_in" of entity "phylite_tester" is not in the component being instantiated - Error (Suppressible): ../../ip/ed_sim/ed_sim_tester_0/sim/ed_sim_tester_0.vhd(93): (vopt-1130) port "channel_strobe_out_in" of entity "phylite_tester" is not in the component being instantiated Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, you might see the above compilation error in the Questa*-Intel® FPGA Edition Software version 2022.1 while running a simulation of the VHDL-based design example of the PHY Lite for Parallel Interfaces Intel Agilex® FPGA IP. This is due to the PHYLITE IP Tester with PRBS Generator and Check contained within the design example that uses the port "channel_strobe_out_in", which is no longer used in the PHY Lite for Parallel Interfaces Intel Agilex® FPGA IP. Resolution To work around this problem, suppress the error by replacing line 127 in the msim_setup.tcl as follow: set USER_DEFINED_ELAB_OPTIONS "-suppress 1130, 14408, 16154" This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v22.2. Custom Fields values: ['novalue'] Troubleshooting 22014676090 22014723001 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.2 22.1 ['Agilex™ 7 FPGAs and SoCs'] ['Simulation Dev Tools Questa'] ['novalue'] ['novalue']