Global Clock & Regional clock inputs in Agilex M FPGA - Global Clock & Regional clock inputs in Agilex M FPGA Hi, Kindly answer the following queries related to reference clocks in F-Tile of Agilex M FPGA. Why F-Tile in Agilex M series FPGA needs four Global Clock input signals & Four regional clock inputs signals ? Why multiple clock inputs of Global clocks and Regional clocks are provided in F-Tile of Agilex M FPGA? Can I drive only one global clock input with 156.25MHz & and use Eight FGT tansceivers (in two quads) in F-Tile to get 400GE ? Or I have to drive at least two global input clocks ? When do we need to drive regional clock inputs ? When do I need to drive global clock inputs ? In reference design(Agilex M GPGA 3xF-Tile 1xR-Tile based), two clocks of different values(390.625MH, 156.25MHz) are driving the reference clock inputs. Why ? Regards, Thulasi Replies: Re: Global Clock & Regional clock inputs in Agilex M FPGA Dear Customer, I'm glad that your issue is resolved. I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Best regards, Altera Technical Support Replies: Re: Global Clock & Regional clock inputs in Agilex M FPGA Hi, Based on the F-tile architecture and the SyncE operation. 1. Is SyncE clock recovery supported only on the FGT PMAs in Quad-2 and Quad-3? Yes. The SyncE section says the recovered clock from the FGT PMA can be driven to dedicated clock output pins, and that each F-Tile has only two such outputs: FGT Quads 2 and 3 . The architecture guide further says one RX CDR clock output must come from Quad 2 and the other from Quad 3 . 2. Is it not possible to recover the SyncE clock from transceivers in Quad-0 and Quad-1? Correct for the dedicated SyncE recovered-clock output path. Public docs say the “Enable dedicated CDR clock output” option is available only for Ports 8–15 , which map to FGT Quads 2 and 3 , not Quads 0 and 1. 3. Is SyncE clock recovery supported on FHT PMAs, or only FGT PMAs? Based on the public F-Tile docs, it is only documented for FGT PMAs . The Ethernet SyncE chapter and the architecture chapter both describe FGT RX CDR clock output ; the FHT clocking chapter describes FHT reference-clock inputs/common PLLs, not a corresponding SyncE recovered-clock output path. 4. Which F-Tile transceiver types and quads support SyncE clock recovery? Supported for SyncE recovered-clock output: FGT , Quad 2 and Quad 3 only. Not supported for that output path: FGT Quad 0/1 and FHT PMAs . Refer: https://docs.altera.com/r/docs/683872/26.1/f-tile-architecture-and-pma-and-fec-direct-phy-ip-user-guide/fgt-and-system-pll-reference-clock-network https://docs.altera.com/r/docs/683023/25.3.1/f-tile-ethernet-hard-ip-user-guide/clock-connections-in-synchronous-ethernet-operation Regards Replies: Re: Global Clock & Regional clock inputs in Agilex M FPGA Hi, I have a question regarding SyncE clock recovery in the Agilex M F-Tile transceivers. 1. Is SyncE clock recovery supported only on the FGT PMAs in Quad-2 and Quad-3 (the eight FGT transceiver channels)? 2. Is it not possible to recover the SyncE clock from the transceivers in Quad-0 and Quad-1 ? 3. Is SyncE clock recovery supported on the FHT PMAs in the F-Tile, or is it limited to the FGT PMAs? Could you please clarify which F-Tile transceiver types and quads support SyncE clock recovery? Regards, Thulasi Replies: Re: Global Clock & Regional clock inputs in Agilex M FPGA Hi, Are you referring to the Agilex™ 7 FPGA M-Series Development Kit - HBM2e Edition (3x F-Tile & 1x R-Tile)? If so, it is a generic dev kit. Clocks of different frequencies drive different reference clocks and there sources are also different. It just provides flexibility to the user to choose a clock as they need. For example, tile 13A, refclk 4 (pin DJ14) is driven by CLK_390_625MHZ_2P, 390.625MHz clock. The source of it is SI5518 IC. At the same time the refclk 5 is driven by a 156.25MHz clock at pin DE14, source SI5394. Note that both SI5518 and SI5394 can also be modified to drive any other frequency using the clock controller tool. Depending on your application requirement you may choose either of the clock. An example scenario could be: quad 2 channels require 390.625MHz refclk let's say, so you choose refclk 4. At the same time, quad 3 channels may require 156.25MHz refclk, so you choose refclk 5. Regards Replies: Re: Global Clock & Regional clock inputs in Agilex M FPGA Hi, Thanks for the response. When two clocks of different values(390.625MHz & 156.25MHz at ref 2, 3) are required at the reference clock inputs of F-Tile ? It is observed in Agilex M/I based designs. Regards Replies: Re: Global Clock & Regional clock inputs in Agilex M FPGA Hi, The F-tile transceiver channels are grouped in quads i.e. 4 channels in a group. Not all the reference clocks reach each of the FGT and FHT channel. You need not necessarily drive multiple reference clocks. Drive one of the global clocks that reach all the FGT channels i.e. either of Refclk 2, 3, 4 and 5 if all the channels you use can share the same frequency. Similarly FHT quad has its own refclk network. Kindly refer to the Reference Clock Network section of the F-tile Architecture user guide: https://docs.altera.com/r/docs/683872/26.1/f-tile-architecture-and-pma-and-fec-direct-phy-ip-user-guide/reference-clock-network Regards