Is there a known issue when simulating the Arria® 10 FPGA I/O PLLs? - Is there a known issue when simulating the Arria® 10 FPGA I/O PLLs? Description Yes, due to a simulation model bug, you might encounter an error when simulating a design with an instance of the Arria® 10 FPGA I/O PLL using the Quartus® Prime Pro Edition Design Software Version 24.3 and below, as well as with the Quartus® Prime Standard Edition Design Software Version 24.1 and below. The root cause of the issue is a difference in the naming of a parameter in the twentynm_clkena module. The failing signature might indicate a compilation error when simulating the design. Resolution This issue is fixed in Quartus® Prime Pro Edition Design Software Version 25.1 and Quartus® Prime Standard Edition Design Software Version 25.1. Alternatively, if a patch for an older version is needed, please file a request with an Altera Premier Support case. Custom Fields values: ['novalue'] Troubleshooting 22020903917 False ['IOPLL IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1 24.3 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']