Why do I get the critical warning when I assigned GPIOs on I/O Bank 2 on MAX® 10 with the analog-to-digital converter (ADC) project? - Why do I get the critical warning when I assigned GPIOs on I/O Bank 2 on MAX® 10 with the analog-to-digital converter (ADC) project? Description You will get the critical warning message " Critical Warning(16248) Pin XYZ is placed too close with ADC pins " when you assign GPIO pins to I/O Bank 1A, 1B, 2, and 8 with an analog-to-digital converter (ADC) block being used in MAX® 10 E144 package device. Resolution Please refer to Table 19 from the MAX® 10 General Purpose I/O User Guide : Please refer above table to assign the GPIO pins to the correct I/O banks. Custom Fields values: ['novalue'] Troubleshooting 15015532473 False ['Modular ADC core IP'] ['FPGA Dev Tools Quartus® Prime Software QUARTUS-ALITE'] 24.1 22.1 ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']