Why do I see link up issues when using the F-Tile Serial Lite IV Intel® FPGA IP FHT PMA variants at NRZ F50G and PAM4 F100G? - Why do I see link up issues when using the F-Tile Serial Lite IV Intel® FPGA IP FHT PMA variants at NRZ F50G and PAM4 F100G? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, you might encounter link-up issues when using the F-Tile Serial Lite IV Intel® FPGA IP FHT PMA variants at NRZ F50G and PAM4 F100G when running the design example system console TCL. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, after generating the F-Tile Serial Lite IV Intel® FPGA IP Design Example, replace the lanes calculation expression as shown below in the ed_hwtest/system_console/sliv_ftile.tcl file. FHT NRZ 48G-58G : proc wait_for_pcs_ready { } { … Line 201 : set actual_lane $lanes → set actual_lane [expr $lanes >> 1] … } proc sl4_link_init_int_lpbk {val} { … Line 1071 : set real_lanes $lanes → set real_lanes [expr $lanes >> 1] … } FHT PAM4 96G-116G : proc wait_for_pcs_ready { } { … Line 199: set actual_lane [expr $lanes >> 1 ] → set actual_lane [expr $lanes >> 2] … } proc sl4_link_init_int_lpbk {val} { … Line 1068: set real_lanes [expr $lanes >> 1 ] → set real_lanes [expr $lanes >> 2] … } This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.3. Custom Fields values: ['novalue'] Errata 15011351460 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 22.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']