What is the transceiver channel numbering scheme within a bank for Stratix V transceiver devices? - What is the transceiver channel numbering scheme within a bank for Stratix V transceiver devices? Description Each transceiver bank in Stratix® V devices is numbered in multiples of six channels per bank where the lowest numbered pin name equates to channel 0 of that bank, and increments sequentially to channel 5 for the highest numbered pin name of that bank. The following example shows the numbering scheme for a 5SGXEA7K3F40C device with three transceiver banks per side of the device. Bank B2[L,R] GXB_[Tx,Rx]_[L,R]17 = Ch 5 within bank GXB_[Tx,Rx]_[L,R]16 = Ch 4 within bank GXB_[Tx,Rx]_[L,R]15 = Ch 3 within bank GXB_[Tx,Rx]_[L,R]14 = Ch 2 within bank GXB_[Tx,Rx]_[L,R]13 = Ch 1 within bank GXB_[Tx,Rx]_[L,R]12 = Ch 0 within bank Bank B1[L,R] GXB_[Tx,Rx]_[L,R]11 = Ch 5 within bank GXB_[Tx,Rx]_[L,R]10 = Ch 4 within bank GXB_[Tx,Rx]_[L,R]9 = Ch 3 within bank GXB_[Tx,Rx]_[L,R]8 = Ch 2 within bank GXB_[Tx,Rx]_[L,R]7 = Ch 1 within bank GXB_[Tx,Rx]_[L,R]6 = Ch 0 within bank Bank B0[L,R] GXB_[Tx,Rx]_[L,R]5 = Ch 5 within bank GXB_[Tx,Rx]_[L,R]4 = Ch 4 within bank GXB_[Tx,Rx]_[L,R]3 = Ch 3 within bank GXB_[Tx,Rx]_[L,R]2 = Ch 2 within bank GXB_[Tx,Rx]_[L,R]1 = Ch 1 within bank GXB_[Tx,Rx]_[L,R]0 = Ch 0 within bank Related Articles Can I place bonded transceiver channels non-contiguously in Stratix V and Arria GZ transceiver devices? Are there any channel placement restrictions when implementing bonded transceiver channels using the Quartus II Software for Stratix V GX, GS, and GT devices? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']