Using the Nios® II Processor: Hardware Development (Legacy Course) - 27 Minutes Learn about the Nios® II embedded soft processor v. 14.1. Learn the basics of the Avalon® Interface Specification and the Platform Designer high performance network-on-a-programmable-chip architecture. Learn to use the Platform Designer system integration tool to develop & configure customized Nios II processor-based hardware systems. Utilize the associated Nios II processor and Platform Designer “Hello World” lab on the Altera® MAX® 10 device development kit to exercise the concepts discussed in the slides and associated tool demonstrations included in this class. Course Objectives At course completion, you will be able to: Configure the Nios II embedded processor using the Altera® Quartus® Prime Software and Platform Designer tool Generate Nios II processor hardware description language (HDL) output files from the Platform Designer tool Skills Required Background in digital logic design Working knowledge of the Altera® Quartus Prime Software Some knowledge of programming in C for embedded systems If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ONIIHW. FPGA_ONIIHW. <p>Using the Nios II Processor: Hardware Development</p>