Using Fast Forward Compile for HyperFlex® Architecture - 30 Minutes In the Using Fast Forward Compile for the Hyperflex® Architecture course, you will learn how to use Fast Forward Compile, a Quartus® Prime Pro software analysis tool that provides design performance recommendations with specific design changes you can make to improve the clock speeds of your Agilex ™ series or Stratix® 10 FPGA designs. In this training, you will learn how to run Fast Forward analysis and how to read its output reports that will allow you to plan design changes and estimate the performance gains you can achieve if the corresponding changes are implemented. As a result, you as a designer will know exactly where to invest design effort to achieve your target design goals Course Objectives At course completion, you will be able to: Enable and run a Fast Forward compile in Quartus Prime Pro software Use the results of Fast Forward compile to achieve required performance gains Skills Required Familiarity with FPGA/CPLD design flow Familiarity with Quartus Prime Pro design software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OS10FFC. FPGA_OS10FFC. <p>Using Fast Forward Compile for HyperFlex Architecture</p>