Error (16270): The following 2 non-mergeable IOPLLs are driving the clkctrl block - Error (16270): The following 2 non-mergeable IOPLLs are driving the clkctrl block Description You may receive this error message in the Quartus® II software if you are feeding the outputs of two IOPLLs into a Clock Control (ALTCLKCTRL) block, in Arria® 10 devices. In Arria 10 devices, the IO tiles only contain 1 PLL each. A Clock Control block can only select from local clock sources, so if Quartus II cannot merge the IOPLLs into a single location, this error will be given. Resolution If you need to feed the outputs from more than one PLL into a Clock Control block, consider using fPLLs, since there are two fPLLs in a HSSI tile. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL'] ['novalue'] novalue novalue ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']