Why are my SOPC Builder clocks undefined in simulation when using ALTPLL in SOPC Builder to generate these clocks? - Why are my SOPC Builder clocks undefined in simulation when using ALTPLL in SOPC Builder to generate these clocks? Description This is a known issue with Quartus® II software version 10.x, and is associated with the definition of 'pfdena' in the ALTPLL megafunction when "Created an 'pfdena' input to selectively enable the phase/frequency detector" is not enabled in this megafunction. The workaround this issue enable this option in your ALTPLL function within your SOPC Builder system. This can be done by: Open your SOPC Builder system Select the ALTPLL block, and select Edit In the ALTPLL block, go to page 2 (Inputs/Lock) and enable "Create an 'pfdena' input to selectively enable the phase/frequency detector". Click Finish, Finish in the ALTPLL block. Regenerate the SOPC Builder system. Select Run Simulation from SOPC Builder - being sure that SOPC Builder Tool > Options... HDL Simulator Options path is properly set. This issue will be fixed in a future version of Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']