Cyclone 10 LP I/O pins configuration - Cyclone 10 LP I/O pins configuration Hello, I am working with a custom PCB that includes a Cyclone 10 LP FPGA, and I am using Quartus Prime Lite v20.1.1. On this PCB, some of the output pins drive optical fibers. The problem is that, when the device is powered on, these pins activate all the optical fibers, and I would like to prevent this behavior. In a previous design, we used a MAX 10 FPGA. The attached image shows the Device and Pin Options configuration for the MAX 10. On this page, there is an option called “Set I/O to weak pull-up prior to user mode.” Disabling this option solved the problem. However, I cannot find this option when configuring the Cyclone 10 LP. Does this option exist for the Cyclone 10 LP? If not, how can I configure the device to avoid this behavior? Best regards, Francisco Replies: Re: Cyclone 10 LP I/O pins configuration Hello, Thanks FvM and AqidAyman_Altera for your replies. Using 1k pull-down resistors solved our problem. Best regards, Francisco Replies: Re: Cyclone 10 LP I/O pins configuration Yes, FvM is correct. You can refer to this configuration sequence where the I/O pins are tied to an internal weak pull-up when the device is powered on. Replies: Re: Cyclone 10 LP I/O pins configuration Hi Francisco, pin options become active after loading configuration bistreams. In unconfigured state, FPGA IO pins are still driven by weak pull-up and can produce unwanted output signals. There are two ways to overcome the situation: Change logic polarity to active-low Use strong pull-down resistors (e.g. 0.5 - 1k) to override pull-up. Regards Frank