Configuring the Altera® FPGA E-Tile Hard IP for Ethernet - Same Course in Japanese: イーサネット向けインテル® FPGA Eタイルハード IPのコンフィグレーション 17 Minutes This online course will introduce the IP core used to customize the Hard IP for Ethernet block found in Altera® Agilex ® 7 F-Series and Altera® Stratix® 10 FPGA MX/TX/DX FPGA E-Tiles. The course begins with a description of the optional various configurations of the core that are supported. It then defines some of the features you can select when customizing the core for your target design. The course ends with showing you how to use the parameter editor found in the IP Catalog of the Altera® Quartus® Prime Pro to perform those customizations. Course Objectives At course completion, you will be able to: Describe the features and functionality of the Hard IP for Ethernet found in Altera® Agilex ® 7 F-Series and Altera® ® Stratix® 10 FPGA MX/TX/DX FPGA E-Tiles Customize your own Hard IP for Ethernet using the IP Catalog of the Altera® Quartus® Prime Pro software Skills Required Understanding of the Ethernet protocols, particularly 10G, 25G and 100G Ethernet Familiarity with FPGA/CPLD design flow Familiarity with the Altera® Quartus Prime design software Familiarity with Altera® FPGA E-Tile architecture OR viewing the following course: "Altera® FPGA E-Tile Transceiver Basics" If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OS10HETILE. FPGA_OS10HETILE. <p>Configuring the Altera FPGA E-Tile Hard IP for Ethernet</p>