Why does the .pin file show a VREF voltage requirement against the VREFB pins when using Differential SSTL/HSTL/HSUL I/O standards in Agilex™ 7 devices? - Why does the .pin file show a VREF voltage requirement against the VREFB pins when using Differential SSTL/HSTL/HSUL I/O standards in Agilex™ 7 devices? Description Due to a problem in Quartus® Prime Pro Edition Software version 23.2 and earlier, the .pin file incorrectly shows a VREF voltage of 0.6V against the VREFB pins when using Differential SSTL/HSTL/HSUL I/O standards in Agilex™ 7 devices. These I/O standards do not require an external VREF. Resolution You may ignore the external VREF voltage requirement if using Differential SSTL/HSTL/HSUL I/O standards. This problem is fixed starting from Quartus® Prime Pro Edition Software version 24.1 Custom Fields values: ['novalue'] Troubleshooting 18031005239; 14020359250 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 22.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']