Low-Latency 10G Ethernet MAC - MLE FPGA IP Core Design - The 10G Ethernet MAC IP Core from Fraunhofer Heinrich Hertz Institute is a low latency Ethernet Media Access Controller (MAC) according to IEEE802.3 -2008 specification. The IP Core was specifically… Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Stratix® III FPGA Stratix® IV GX FPGA Stratix® V GS FPGA . Aerospace ASIC Proto Data Center Cloud (Public, Private, Hybrid) Defense Industrial Test Low-Latency 10G Ethernet MAC - MLE FPGA IP Core Design Key Features Platform and device vendor independent core Offering Brief No No No Yes Encrypted Verilog Encrypted VHDL Verilog VHDL Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Stratix® III FPGA Stratix® IV GX FPGA Stratix® V GS FPGA No No 25.1.1 Offering Brief Production a1JUi0000062RiDMAU What's Included Fully paid-up-for Single-Project or Multi-Project Use IP Core license for FPGA; delivered as encrypted netlist or RTL. Ordering Information 10G-MAC a1JUi0000062RiDMAU Production Design Services Intellectual Property (IP) a1MUi00000BO8sfMAD a1MUi00000BO8sfMAD Select 2025-10-31T21:42:53.000+0000 The 10G Ethernet MAC IP Core from Fraunhofer Heinrich Hertz Institute is a low latency Ethernet Media Access Controller (MAC) according to IEEE802.3 -2008 specification. The IP Core was specifically designed to have the lowest possible latency, and to be as resource efficient as possible at the same time. Partner Solutions - 2026-03-10
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