A Full 4K Vision Pipeline in a Cost-Optimized FPGA? Agilex® 3 Shows What is Possible - A Full 4K Vision Pipeline in a Cost-Optimized FPGA? Agilex® 3 Shows What is Possible Smart cameras and embedded vision systems are being asked to do more at the edge. They need to capture higher-resolution video, process images in real time, support evolving sensors and interfaces, and prepare clean data for analytics or AI. At the same time, many of these systems are constrained by board area, system cost, power budgets, and long product lifecycles. That combination creates a familiar engineering challenge: how much of a real vision pipeline can be built in a device class optimized for lower logic density and cost? The Agilex® 3 4Kp30 Camera Lite reference design gives a compelling answer. It demonstrates a practical sensor-to-display camera pipeline built on Agilex 3, showing how a power- and cost-optimized FPGA can ingest a 4K image stream over MIPI CSI-2, process raw sensor data through an image signal processing pipeline, and output 4Kp30 video through DisplayPort 1.4. The reference design is a complete working vision pipeline that you can use to build your own based on your unique requirements. From sensor input to display output The reference design starts with a Raspberry Pi High Quality Camera module using the Sony IMX477 image sensor. The sensor outputs 12-bit raw Bayer data and connects to the FPGA through a MIPI CSI-2 interface. From there, the MIPI CSI-2 IP converts the incoming pixel stream into AXI4-Streaming data, making it available to the rest of the Altera® Video and Vision Processing (VVP) Suite pipeline. Inside the FPGA fabric, the design implements the major stages needed to turn raw sensor data into display-ready video. The ISP pipeline includes Black Level Correction, White Balance Correction, Demosaic, Color Correction Matrix, and a 1D LUT. The pipeline supports 12-bit raw data up to the Demosaic IP and 10-bit RGB for downstream video processing. The result is a fixed 3840 x 2160, 30 Hz video path from camera input to display output. That matters because many real products need more than a way to receive camera data. They need image correction, color processing, buffering, video formatting, display output, and software control. Agilex 3 brings those pieces together in a reference design that engineers can study, run, and adapt. A practical foundation for smart camera products For security cameras, industrial vision, smart infrastructure, robotics, retail analytics, and access control, the camera pipeline is often the first major design decision. The system must bring pixels in from the sensor, correct and format them, keep timing deterministic, and deliver data to the next stage of the product. In many cases, that next stage may be a display path, a host processor, a networking subsystem, a storage path, or an AI analytics engine. The Agilex 3 reference design is valuable because it gives developers a working foundation for that pipeline. It demonstrates the sensor input, image-processing path, video frame buffer, output mixer, and DisplayPort output using Altera IP. Developers can use it as a starting point, then adapt the pipeline for their own sensor choice, image-processing requirements, overlay needs, output path, or product-specific differentiation. In the current reference design, the video frame buffer is used for video synchronization. This is a practical detail worth highlighting because real video designs often need buffering for timing alignment, rate matching, format conversion, or system-level processing. The design uses external LPDDR SDRAM through an external memory interface for that frame buffer. More broadly, Agilex 3 SoC devices also supports LPDDR5 memory interfaces, giving production designs a path to compact memory subsystems around video and embedded processing workloads. Embedded control today, hard processor path for production systems The current Agilex 3 Camera Lite reference design uses a Nios® V soft processor running a bare-metal software application. That software discovers the hardware IP blocks, configures them, monitors feedback loops, and provides a terminal-based interface over JTAG-UART. This is a good fit for the reference design because it keeps the example compact and focused on the FPGA-resident video pipeline. For production smart camera or industrial vision systems, Agilex 3 SoC devices add another important platform option: an integrated hard processor system with dual-core Arm® Cortex®-A55 processors. That HPS is not used in this reference design, but it can be a major advantage in a product architecture. Designers can use the FPGA fabric for deterministic video ingest and image processing while using the HPS for system control, application software, communication stacks, user interfaces, sensor orchestration, security services, or higher-level product logic. This combination is especially important for embedded vision. Hardware pipelines are excellent at moving and processing pixels predictably. Software is excellent at managing the product around that pipeline. Agilex 3 gives designers both paths in the same device family: a fabric-based video processing foundation and, when needed, an integrated Arm-based processing subsystem for production software. A path toward AI-enhanced edge vision The Agilex 3 4Kp30 Camera Lite reference design is not an AI inference design. Its focus is 4K camera ingest, ISP processing, video buffering, output mixing, and DisplayPort output. That distinction is important. At the same time, the architecture points naturally toward smarter edge vision systems. Agilex 3 includes AI-capable Tensor Block architecture in the fabric, and Agilex 3 and Agilex 5 share an architecturally aligned FPGA fabric foundation. The related Agilex 5 camera reference design shows the fuller concept by combining multi-sensor 4K camera input, ISP processing, FPGA AI Suite inference, Linux software on the HPS, and display output with AI results. That gives customers a scalable design story. Agilex 3 can be the cost-optimized starting point for 4K smart camera pipelines and edge vision preprocessing. Agilex 5 can scale the concept to larger, more compute-intensive designs that integrate AI inference directly into the reference architecture. Customers can begin with the 4K vision pipeline they need today and scale toward more intelligent camera systems as product requirements evolve. Why it matters The real message of the Agilex 3 4Kp30 Camera Lite reference design is: a lower-density, cost-optimized FPGA can still implement a substantial portion of a modern vision system using available Altera IP. That includes native camera ingest, AXI4-Streaming video movement, ISP processing, frame buffering, output mixing, embedded software control, and DisplayPort output. For customers building smart cameras, industrial vision systems, surveillance endpoints, or edge AI preprocessing pipelines, this is a practical starting point rather than a blank page. With Agilex 3, designers can build compact, customizable 4K vision systems while keeping a clear path to hard processor integration, modern memory support, and future AI-enhanced processing. It is a strong example of how much capability can fit into the power- and cost-optimized segment of the Agilex portfolio. Explore the Agilex 3 4Kp30 Camera Lite reference design and use it as a starting point for your next smart camera, industrial vision, surveillance, or edge AI preprocessing system. Source links for reviewers Agilex 3 4Kp30 Camera Lite developer documentation Agilex 3 camera GitHub repository Agilex 3 FPGAs and SoCs device overview Agilex 3 HPS documentation Agilex 5 4Kp30 Multi-Sensor Camera with AI Inference documentation