Error(19300): DSP WYSIWYG primitive "dafloater_i|s10fpdsp_block_0|sp_mult" has clock setting "adder_input_clock" that is not set to "none". - Error(19300): DSP WYSIWYG primitive "dafloater_i|s10fpdsp_block_0|sp_mult" has clock setting "adder_input_clock" that is not set to "none". Description Due to a problem with the Stratix® 10 Native Floating Point DSP IP in Quartus® Prime Pro software version 17.1 Stratix 10 ES Edition, you may observe the above error during compilation if you are using the multiplication mode. Resolution Do the following changes in the <ip_file_name>_altera_s10fpdsp_block_160_mdhrmmi.sv: from .adder_input_clock("0") //(line 28) to .adder_input_clock("NONE") This problem is fixed starting in Quartus Prime Pro v17.1 release software. Custom Fields values: ['novalue'] Troubleshooting FB: 492683; False ['DSP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.1 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']