Why does DSP builder advance synthesisInfo block fail to constrain the latency when it is specified? - Why does DSP builder advance synthesisInfo block fail to constrain the latency when it is specified? Description When using the synthesisInfo block in the DSP Builder Advanced library, the latency can only be constrained between the ChannelIn and ChannelOut block. Resolution If you are using GPIN and GPOUT bock as an interface to your subsystem, the synthesisInfo block latency constraint will not be taken into account, unless they are replaced by a pair of ChannelIn and ChannelOut block. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Programmable Logic Devices'] ['DSP Builder for Pro Edition'] ['novalue'] ['novalue']