Error(11193): Output port "OUTCLK[<number>]" of "CMU_FPLL" cannot connect to PLD port "I[<number>]" of "IO_OUTPUT_BUFFER" for node "<pin name>". - Error(11193): Output port "OUTCLK[<number>]" of "CMU_FPLL" cannot connect to PLD port "I[<number>]" of "IO_OUTPUT_BUFFER" for node "<pin name>". Description Due to a problem in Quartus® Prime Pro Edition Software versions 22.3 to 23.3, you will see this error when a clock output of an FPLL is connected to an output pin using 2.5 V, 3.0-V LVTTL or 3.0-V LVCMOS I/O standards in Arria® 10 and Cyclone® 10 GX devices. Resolution This problem has been fixed starting from Quartus® Prime Pro Edition software version 23.4 Custom Fields values: ['novalue'] Troubleshooting 15016209480 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.4 22.3 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']