PCIe to SRIO Bridge Controller (FPGA IP for Altera Devices) - This Gen3 PCIe to SRIO Bridge enables full-speed protocol conversion with advanced messaging and DMA engines. Supporting aerospace, telecom, defense, and HPC, it ensures low-power, compact… Mobiveil, Inc.(a GlobalLogic company) is a fast-growing technology company headquartered in Santa Clara, California, specializing in Silicon Intellectual Properties (SIP), application platforms, and… Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® V GS FPGA Stratix® V GX FPGA High-performance protocol bridge IP connecting x4 PCIe Gen3 ↔ x4 SRIO Gen3, with configurable x4/x2/x1 ports, BRC3 10.3125 Gbaud support, up to 8 DMA channels (2 in Light RAB), deep per-channel buffering, and robust error handling (AER/IER). Technology-independent, system-validated bridge that sustains line-rate transfers (≥64-byte SRIO packets) between PCIe and SRIO. Features include x4/x2/x1 on both PCIe and SRIO, BRC1/BRC2/BRC3 data rates (1.25→10.3125 Gbaud), 8 KB packet buffering per DMA/messaging channel, MSI-X (70 vectors), ECRC, AER/IER, lane reversal and polarity inversion on PCIe, and hot-insert/extract on SRIO. Addressing supports RIO 34/50/66-bit and AXI 32/38/64-bit; clocking at 100/125/156.25 MHz for both endpoints. Delivered with synthesizable Verilog RTL, comprehensive verification environment, and design/user/synthesis guides. Aerospace ASIC Proto Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Industrial Medical Transportation 5G/ 6G Radio AI-RAN Baseband DAS/repeater/RIS NTN/Fixed Wireless PCIe to SRIO Bridge Controller (FPGA IP for Altera Devices) Key Features Bridges x4 PCIe Gen3 to x4 SRIO Gen3, with port scalability to x4, x2, or x1 configurations. Offering Brief No No No No Encrypted Verilog Verilog Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049UK1MAM What's Included Synthesizable RTL design in Verilog HDL Ordering Information NA Direct a1JUi0000049UK1MAM Production Intellectual Property (IP) a1MUi00000BO8shMAD a1MUi00000BO8shMAD Select 2025-10-24T16:13:51.000+0000 This Gen3 PCIe to SRIO Bridge enables full-speed protocol conversion with advanced messaging and DMA engines. Supporting aerospace, telecom, defense, and HPC, it ensures low-power, compact implementation. Ideal for embedded systems, it bridges PCIe versatility with SRIO performance. Partner Solutions