Are the timing violations on the bonding interface of my Cyclone® V or Arria® V DDR3 bonded hard memory controller design valid? - Are the timing violations on the bonding interface of my Cyclone® V or Arria® V DDR3 bonded hard memory controller design valid? Description When bonding two DDR3 hard memory controllers in Cyclone® V or Arria® V, you may experience timing violations on the bonding interface. These violations are valid. Resolution The workaround is to insert pipeline registers for the bonding signals. Custom Fields values: ['novalue'] Troubleshooting 2205866268 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']