Why does my Altera PLL fail to lock in simulation? - Why does my Altera PLL fail to lock in simulation? Description Due to a problem with the Altera PLL simulation model in the Quartus® II software versions 12.0 and earlier, the PLL may fail to lock in simulation if the areset port is not high at the beginning of simulation. This problem affects both gate-level and RTL simulation for designs targeting Stratix® V, Arria® V, and Cyclone® V devices. Resolution To avoid this problem, ensure that simulations using the Altera PLL begin with areset set high. This problem is fixed beginning with the Quartus II software version 12.0 SP1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL', 'Simulation'] ['FPGA Dev Tools Quartus II Software'] 12.0.1 11.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']