How do I use the Fast Simulation Models to improve the simulation time in the Quartus® Prime Pro Edition Software version 24.3.1 onwards? - How do I use the Fast Simulation Models to improve the simulation time in the Quartus® Prime Pro Edition Software version 24.3.1 onwards? Description Follow these steps to use the Fast Simulation Models in designs targeting Agilex™ 7 FPGA, Agilex™ 5 FPGA, or Agilex™ 3 FPGA devices to improve simulation time in the Quartus® Prime Pro Edition Software version 24.3.1 onwards. Resolution Generate the example design from the .ip file or create a custom design for simulation (the same as the current flow). Update the auto-generated simulation script to point to Fast Simulation Models in Agilex™ 7 FPGA, Agilex™ 5 FPGA, or Agilex™ 3 FPGA designs by setting the following variables with either of the following methods: Method 1: For Questasim Update the Tcl-based scripts ( msim_setup.tcl) with the following variables: s et DEVICES_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/../devices/sim_lib2/" set QUARTUS_SIM_LIB_DIR "$QUARTUS_INSTALL_DIR/eda/sim_lib2/" Method 2: For VCS (2-step), VCS (3-step) Update the qsys-generated script (sh based scripts: vcs_setup.sh or vcsmx_setup.sh ) with the following variables: DEVICES_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/../devices/sim_lib2/" QUARTUS_SIM_LIB_DIR="$QUARTUS_INSTALL_DIR/eda/sim_lib2/" Update the auto-generated simulation scripts to remove commands/options that slow down the simulation. Questasim: In the top-level example design simulation script, ensure ld and elab are called (instead of ld_debu g and elab_debug ). Remove -voptargs=+acc under elab_debug in mentor/msim_setup.tcl and under proc get_elab_options in common/modelsim_files.tcl if present. Remove commands that dump out waveforms and other commands/options that can slow down the simulation. VCS (2-step), VCS (3-step): Remove any debug elaboration options in the top-level script ( start with -debug_ ) Remove the -kdb option and any elaboration and simulation options to dump waveforms (such as +fsdb or +vpd dumps) The IP example design for these devices has been enabled to use Fast Simulation Models by default in the Quartus® Prime Pro Edition Software version 25.1.1 onwards. Additional Information How do I revert from Fast Simulation Models to the Default Simulation Models in Quartus® Prime Pro Edition Software version 25.1.1 onwards? Custom Fields values: ['novalue'] Troubleshooting 14024060949 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.3.1 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']