Why does the DisplayPort IP core RX link training fail at one or two lanes when transceiver PCS channel bonding is enabled? - Why does the DisplayPort IP core RX link training fail at one or two lanes when transceiver PCS channel bonding is enabled? Description When using the DisplayPort IP core in conjunction with transceivers that have PCS channel bonding enabled, the DisplayPort IP core may see RX bit errors or even see RX link training fail entirely. This can be caused by the "PCS TX channel bonding master" being set incorrectly. To check if the setting is incorrect, open the Arria ® 10 Transceiver Native PHY instantiation in the IP Parameter Editor GUI. Under TX PMA settings, if the “TX channel bonding mode” is set to “PMA and PCS bonding”, check the setting of the “PCS TX channel bonding master”. If it is set to “Auto”, the Transceiver Native PHY IP may automatically select channel 2 as the channel bonding master. Since channel 2 is not driven when the DisplayPort IP core is using fewer than four lanes, this can cause clock recovery issues on the RX side. Resolution To resolve this issue, set the “PCS TX channel bonding master” to 0. Channel 0 is driven at all lane counts, and so this setting avoids this problem. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']