How do I view the external memory signals in my HPS SDRAM simulation? - How do I view the external memory signals in my HPS SDRAM simulation? Description The HPS simulation model does not use external memory pins to connect to the DDR2, DDR3 or LPDDR2 memory model. The actual memory model is created internally in the following hierarchy: hps_0/fpga_interfaces/f2sdram/hps_sdram_inst/mem/ You will need to view the external signals at this level. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Simulation'] ['novalue'] novalue novalue ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']