Error(22728): Synthesis is run on design with Tile IP for instance <...> but the support logic has not been generated. - Error(22728): Synthesis is run on design with Tile IP for instance <...> but the support logic has not been generated. Description You might see this error message at the Synthesis stage when the design uses the . bdf file to instantiate the Tile IP, or you have not ru nthe Quartus® Tile Logic Generation compilation stage. Resolution The .bdf file is not a supported method of instantiating the Tile IP. To avoid this error, instantiate the Tile IP using a Verilog or VHDL file and run the Quartus® Tile Logic Generation compilation stage. Custom Fields values: ['novalue'] Troubleshooting 15013264816 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 23.1 ['Agilex™ FPGA Portfolio'] ['novalue'] ['novalue'] ['novalue']