Why is the clock phase incorrect in my MAX 10 PLL output? - Why is the clock phase incorrect in my MAX 10 PLL output? Description Due to a problem in the Quartus® Prime Standard edition software version 16.0, the Max® 10 ALTPLL IP with phase shift setting will show an incorrect value in the TimeQuest Timing Analyzer clock report. Resolution This problem has been fixed in the Quartus Prime Standard edition software version 16.0 Update 2. Custom Fields values: ['novalue'] Troubleshooting FB: 385649; False ['PLL IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 16.0.2 16.0 ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25