Why does the Avalon bus lock up when simulating a DDR2 SDRAM and DDR3 SDRAM Controller with UniPHY generated in version 11.0? - Why does the Avalon bus lock up when simulating a DDR2 SDRAM and DDR3 SDRAM Controller with UniPHY generated in version 11.0? Description DDR2 SDRAM and DDR3 SDRAM UniPHY based Controller version 11.0 with the Control and Status Register (CSR) Interface enabled causes the Avalon bus to lock up in Modelsim simulations. After an Avalon read or write transaction, the WAITREQUEST signal asserts high and stays asserted indefinitely, not allowing other read or write transactions on the Avalon bus. The problem is in the alt_mem_ddrx_csr.v file. There are bus width mismatches in the file that leads to unconnected bits to certain configuration ports. The workaround is to download the attached version of the alt_mem_ddrx_csr.v file and overwrite the four instances in the following directories: corename/ corename _sim / altera_mem_if_nextgen_ddr3_controller_core/ corename_ example_design/simulation/ corename _example_sim/submodules corename _example_design/example_project/ corename_ example/submodules This issue will be fixed in a future version of the Quartus® II software. Download the Verilog file from the link below: alt_mem_ddrx_csr.v (Verilog) Resolution The workaround is to download the attached version of the alt_mem_ddrx_csr.v file and overwrite the four instances in the following directories: corename/ corename _sim / altera_mem_if_nextgen_ddr3_controller_core/ corename_ example_design/simulation/ corename _example_sim/submodules corename _example_design/example_project/ corename_ example/submodules This issue will be fixed in a future version of the Quartus® II software. Download the Verilog file from the link below: alt_mem_ddrx_csr.v (Verilog) Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']