Why does FPGA configuration fail from HPS on Intel® Stratix®10 SX devices when I configure phase 2 bitstreams in HPS boot first mode? - Why does FPGA configuration fail from HPS on Intel® Stratix®10 SX devices when I configure phase 2 bitstreams in HPS boot first mode? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.3, phase 2 bitstream core.rbf configuration from HPS as part of an HPS boot first mode may fail for designs targeting Intel Stratix® 10 SX devices. The following errors may be seen: fpga_manager fpga0: Error while writing image data to FPGA failed to load fpga image OF: overlay: of_overlay_create: Pre-apply notifier failed (err=-110) create_overlay: Failed to create overlay (err=-110) Resolution This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 20.2 and onwards. To resolve this problem, download and install the latest device manager firmware for the Intel® Quartus® Prime Pro Edition Software 21.1/21.2/21.3/21.4/22.1/22.2/22.3. The latest device manager firmware versions are available from the following link: What is the latest device firmware for Intel® Agilex™ and Intel ® Stratix® 10 devices? Custom Fields values: ['novalue'] Troubleshooting 1507917938 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.2 19.3 ['Stratix® 10 SX FPGA'] ['Embedded Dev Tools SoC Suite'] ['novalue'] ['novalue']