What is the expected behavior of mgmt_waitrequest and the status register when using the Altera PLL Reconfig megafunction? - What is the expected behavior of mgmt_waitrequest and the status register when using the Altera PLL Reconfig megafunction? Description In waitrequest mode, the mgmt_waitrequest signal will assert during PLL reconfiguration or if the PLL is in a loss of lock condition. In polling mode, the status register will be 0 (busy) during PLL reconfiguration or if the PLL is in a loss of lock condition. In waitrequest mode, the mgmt_waitrequest signal will de-assert when PLL reconfiguration is complete. If the PLL loses lock after reconfiguration is complete, the mgmt_waitrequest signal will become asserted again until the PLL is locked. There may be a brief period after PLL reconfiguration is complete, but before the PLL has lost lock when mgmt_waitrequest will be de-asserted. In polling mode, the status register will change from 0 (busy) to 1 (not busy) when PLL reconfiguration is complete. If the PLL loses lock after reconfiguration is complete, the status register will become 0 (busy) again until the PLL is locked. There may be a brief period after PLL reconfiguration is complete, but before the PLL has lost lock when the status register will be 1 (not busy). Resolution Intel recommends allowing sufficient time for the PLL to lock after PLL reconfiguration is complete prior to performing a new Avalon read or write operation. Custom Fields values: ['novalue'] Troubleshooting 2205752658 False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']