Questa compile failure - Questa compile failure Dear Support/Expert I have a Quartus project which compiled no problem, the same code while I try to compile with Questa, I will have some errors. which is not directly related to the source code. I guess I need someone who familiar with Questa to have a look at this. the error messsage is # ** Error: (vopt-31) Unable to unlink file "C:/FPGA/TSW14J57_pro/copy3/prj/mentor/libraries/work/@_opt/_data/exempt30nk3y". # Permission denied. (errno = EACCES) Thank you for your help. David following are few more lines to provide a context. # ** Warning: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(40): (vopt-2241) Connection width does not match width of port '<protected>'.<protected> # ** Warning: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(40): (vopt-2241) Connection width does not match width of port '<protected>'.<protected> # ** Error: (vopt-31) Unable to unlink file "C:/FPGA/TSW14J57_pro/copy3/prj/mentor/libraries/work/@_opt/_data/exempt30nk3y". # Permission denied. (errno = EACCES) # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_rx_top.sv(909): (vopt-2685) [TFMPC] - Too few port connections for 'i0_Jesd204b_mc_rx'. Expected 52, found 51. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_rx_top.sv(909): (vopt-2718) [TFMPC] - Missing connection for port 'jesd204_rx_avs_waitrequest'. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_rx_top.sv(975): (vopt-2685) [TFMPC] - Too few port connections for 'i1_Jesd204b_mc_rx'. Expected 52, found 51. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_rx_top.sv(975): (vopt-2718) [TFMPC] - Missing connection for port 'jesd204_rx_avs_waitrequest'. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_rx_top.sv(1193): (vopt-2685) [TFMPC] - Too few port connections for 'jesd_dec_xcvr_0'. Expected 48, found 47. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_rx_top.sv(1193): (vopt-2718) [TFMPC] - Missing connection for port 'rx_std_clkout'. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_tx_top.sv(333): (vopt-2685) [TFMPC] - Too few port connections for 'u_tx_transport'. Expected 24, found 20. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_tx_top.sv(333): (vopt-2718) [TFMPC] - Missing connection for port 'jesd204_tx_link_error'. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_tx_top.sv(333): (vopt-2718) [TFMPC] - Missing connection for port 'csr_n'. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_tx_top.sv(333): (vopt-2718) [TFMPC] - Missing connection for port 'csr_f'. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_tx_top.sv(333): (vopt-2718) [TFMPC] - Missing connection for port 'jesd204_tx_controlin'. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_tx_top.sv(660): (vopt-2685) [TFMPC] - Too few port connections for 'i0_Jesd204b_mc_tx'. Expected 48, found 47. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_tx_top.sv(660): (vopt-2718) [TFMPC] - Missing connection for port 'somf'. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_tx_top.sv(733): (vopt-2685) [TFMPC] - Too few port connections for 'i1_Jesd204b_mc_tx'. Expected 48, found 47. # ** Warning: C:/FPGA/TSW14J57_pro/copy3/ip/ip/jesd204b/jesd204b_jesd_top_qsys_0/jesd_top_qsys_10/sim/jesd_tx_top.sv(733): (vopt-2718) [TFMPC] - Missing connection for port 'somf'. # ** Warning: (vopt-31) Unable to unlink file "C:/FPGA/TSW14J57_pro/copy3/prj/mentor/libraries/work/@_opt/_data/exempt30nk3y". # Access is denied. (GetLastError() = 5) # ** Warning: (vopt-133) Unable to remove directory "C:/FPGA/TSW14J57_pro/copy3/prj/mentor/libraries/work/@_opt/_data". # ** Warning: (vopt-133) Unable to remove directory "C:/FPGA/TSW14J57_pro/copy3/prj/mentor/libraries/work/@_opt". # The directory is not empty. (GetLastError() = 145) # ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=35, Warnings=2175. # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./msim_run.do PAUSED at line 189 Replies: Re: Questa compile failure Why is this an acceptable solution? Aren't we a community of problem solvers? ?This is highlighting an issue with the software. Replies: Re: Questa compile failure Hi David, I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Best Regards, Sheng p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. Replies: Re: Questa compile failure reboot the computer will solve the problem.