Why does the Low Latency Ethernet 10G MAC Intel® FPGA IP generated design example simulation fail? - Why does the Low Latency Ethernet 10G MAC Intel® FPGA IP generated design example simulation fail? Description Due to a problem with the Intel® Quartus® Prime Pro software version 19.3, the Low Latency 10G MAC Intel® FPGA IP generated design example may encounter the above problem. This is because the simulation model outputs an "X" (undefined) instead of valid data, this causes the block lock signal to de-assert and the simulation then stops. Resolution This problem has been fixed starting in the Intel® Quartus® Prime Pro Edition software version 19.4. Custom Fields values: ['novalue'] Troubleshooting 1507396739 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.4 19.3 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']