Why do I see timing violations between the F-Tile Dynamic Reconfiguration Suite IP and the F-Tile Avalon-Streaming IP for PCI Express* when using Quartus® Prime Pro Edition version 25.3 and earlier on Agilex® 7 FPGA devices? - Why do I see timing violations between the F-Tile Dynamic Reconfiguration Suite IP and the F-Tile Avalon-Streaming IP for PCI Express* when using Quartus® Prime Pro Edition version 25.3 and earlier on Agilex® 7 FPGA devices? Description When using Quartus® Prime Pro Edition software version 25.3 and earlier on Agilex® 7 FPGA devices, you might see timing violations between the F-Tile Dynamic Reconfiguration Suite IP and the F-Tile Avalon-Streaming IP for PCI Express* if the F-Tile Avalon-Streaming IP for PCI Express is instantiated inside a VHDL generate statement. This leads to incorrect timing assignments, which may be ignored. Resolution To work around this problem, you can instantiate the F-Tile Avalon-Streaming IP for PCI Express outside of any VHDL generate construct. This problem may be fixed in a future version of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 18044244642 novalue ['Interfaces PCIe'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']