CPRI MegaCore Function Variations That Target an Arria V or a Stratix V Device Require Additional Constraints - CPRI MegaCore Function Variations That Target an Arria V or a Stratix V Device Require Additional Constraints Description CPRI MegaCore function variations that target an Arria V or a Stratix V device require additional project settings to achieve timing closure. The required constraints prevent timing violations associated with global reset signals in the affected variations. Note that Arria V variations configured to run at CPRI line rates higher than 3072 Mbps are affected by the erratum CPRI MegaCore Function Fails Timing in Arria V GX Devices at Line Rates Above 3072 Mbps . Resolution To avoid this issue, add the following constraints to the Quartus Settings File ( .qsf ) for your Quartus II project: set_instance_assignment -name GLOBAL_SIGNAL OFF -to *local_reset set_instance_assignment -name GLOBAL_SIGNAL OFF -to *rx_digitalreset_serdes_txclk_sync2 set_instance_assignment -name GLOBAL_SIGNAL OFF -to *rx_digitalreset_serdes_rxclk_sync2 set_instance_assignment -name GLOBAL_SIGNAL OFF -to "*cpri_sink:ilane_inst[*].cpri_sink_inst|comb~0" set_instance_assignment -name GLOBAL_SIGNAL OFF -to "*cpri_src:ilane_inst[*].cpri_src_inst|comb~0" This issue will be fixed in a future version of the CPRI MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Arria® V FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']