How do I resolve the problem with an Intel® Stratix® 10 FPGA IOPLL not being able to obtain lock when the input refclk is driven by an output clock from the Intel Stratix 10 FPGA E-Tile? - How do I resolve the problem with an Intel® Stratix® 10 FPGA IOPLL not being able to obtain lock when the input refclk is driven by an output clock from the Intel Stratix 10 FPGA E-Tile? Description The Intel® Stratix® 10 FPGA IOPLL is not being able to obtain lock when the input refclk is driven by an output clock from the Intel Stratix 10 FPGA E-Tile. Resolution You must perform user recalibration of the IOPLL after the output clocks from the Intel Stratix 10 FPGA E-Tile are stable. Holding the Intel Stratix 10 FPGA IOPLL in reset until output clocks from the Intel Stratix 10 FPGA E-Tile are stable or pulsing the reset after the output clocks are stable will not resolve the Intel Stratix IOPLL unlocked state. Custom Fields values: ['novalue'] Troubleshooting 14010270221 False ['IOPLL IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 19.3 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']