Riviera-PRO does not support verification IP VHDL BFMs - Riviera-PRO does not support verification IP VHDL BFMs Description Aldec® Riviera-PRO™ Advanced Verification Platform versions prior to 2014.02 do not support verification IP VHDL bus functional models (BFMs). There is no response to VHDL application programming interface (API) calls, causing simulations to stall until the next test program sequence. Resolution This issue is fixed in Riviera-PRO version 2014.02 and later. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Simulation'] ['FPGA Dev Tools Quartus II Software'] 14.0 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']