How does Quartus know what is voltage on each FPGA I/O bank? - How does Quartus know what is voltage on each FPGA I/O bank? It is possible to connect different voltages to each bank of an FPGA. The I/O standard of the pins on the FPGA relies on what bank voltage has been connected to it. Now my questions are: 1. How does Quartus know what voltage is connected to the banks? 2. If Quartus does not know the voltage on the banks, how does it know what I/O standard can be applied on the I/O pins? 3. What constraints exist on what voltage can be supplied to the banks in an FPGA? I am using a MAX10 10M50DAF device. However, a general purpose answer is preferred on this website. Replies: Re: How does Quartus know what is voltage on each FPGA I/O bank? We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Replies: Re: How does Quartus know what is voltage on each FPGA I/O bank? To New Contributor I, In the Pin Planner you specify what voltage goes to each I/O bank. This is done on a pin-by-pin basis. It will give you a (compilation) error if you specify pins with two different voltages on the same bank. It's up to you to connect the correct voltage to each I/O bank on your circuit board. Replies: Re: How does Quartus know what is voltage on each FPGA I/O bank? Hello, The video that I shared with you is just an overview of how Chip Planner work on Intel Quartus software. We have a lot of selections of FPGAs and different I/O Standards thus Quartus show a lot of I/O standards options. However, you can only set specifications based on I/O Standards that you pick on your design or else you will receive errors. To answer your question, the valid input is what the FPGA pins can handle on the specified I/O Standards. I hope this answer your question. Thank you. Replies: Re: How does Quartus know what is voltage on each FPGA I/O bank? Please clarify what part of the video are referring to in your previous message. Also, is a valid input simply what the FPGA pins can handle or what is actually a function of the bank voltage? If the I/O bank is supplied by 3.3V supply then the pin planner should not even show the option to specify a 1.8V I/O standard for any pin on it. I don't think this is how pin planner works. Replies: Re: How does Quartus know what is voltage on each FPGA I/O bank? Hello, Is all of your questions addressed? I will need to close this case if there is no update from you in 3 days. Thanks. Replies: Re: How does Quartus know what is voltage on each FPGA I/O bank? Hello, It will be invalid if your setting does not meet the specifications of the device. We have a lot of tutorial videos about using Quartus on our Intel FPGA Youtube channel. Here is the video about Chip Planner in Quartus Prime Pro Software: https://www.youtube.com/watch?v=Bt-yDRReKZw Thanks Replies: Re: How does Quartus know what is voltage on each FPGA I/O bank? How does it know if it is invalid? I never told it what voltage supply I connected to the bank to begin with. There is no option where we can specify what voltage supply is connected per bank on the FPGA. None. Replies: Re: How does Quartus know what is voltage on each FPGA I/O bank? If you select an invalid I/O standard voltage for your device, you'll get an error during compilation. Replies: Re: How does Quartus know what is voltage on each FPGA I/O bank? Please check the attached image. It shows the available options for the pin I/O standards. The options are all over the place. If Quartus knew that my I/O bank was lets say at 3.3V, it won't show me all those 1.0V and 2.5V options in the drop down menu. Do you understand my question now? Replies: Re: How does Quartus know what is voltage on each FPGA I/O bank? Hello, Thank you for using out Intel® FPGA. That can all be done by using tools in Intel® Quartus®. Everything is done manually where you decide the I/O Standard of your design and then there will be a value(s) of voltage that is allowed on that particular I/O Standard that you have set. You can refer to document from this link on page 9: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_gpio.pdf Like example from the table on page 9: If you pick 3.3V LVCMOS you are allowed to put 3.3V/3.0V/2.5V for Vccio input and 3.3V output. There is no guarantee that you device will be okay if you set beyond the recommended voltage from the document above. I hope this answer helps. Thank you.