Are the Intel® Stratix® 10 device SDM_IO pins configured as open drain when used as PWRMGT_SDA and PWRMGT_SCL for SmartVID PMBus Power Management? - Are the Intel® Stratix® 10 device SDM_IO pins configured as open drain when used as PWRMGT_SDA and PWRMGT_SCL for SmartVID PMBus Power Management? Description Yes, the SDM_IO pins on Intel® Stratix® devices will be configured as open drain when used as PWRMGT_SDA and PWRMGT_SCL for SmartVID PMBus Power Management. Resolution This information has been added to the Intel® Stratix® 10 Device Family Pin Connection Guidelines starting from version 2020.04.20 Custom Fields values: ['novalue'] Troubleshooting 1809368854 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 18.0 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue'] - 2022-01-19