When using Windows* why does the Intel® FPGA P-Tile Avalon® Memory Mapped IP for PCI* Express Example Design fail to generate? - When using Windows* why does the Intel® FPGA P-Tile Avalon® Memory Mapped IP for PCI* Express Example Design fail to generate? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software Windows* version 20.1, the Intel® FPGA P-Tile Avalon® Memory Mapped IP for PCI Express* Example Design will fail to generate in Gen4x4 Root Port mode. Resolution The example design can be generated correctly by the Linux* version of the Intel® Quartus® Prime Pro Edition software version 20.1. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.4. Custom Fields values: ['novalue'] Troubleshooting 1508033530 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.4 20.1 ['Stratix® 10 DX FPGA', 'Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']