Why does my Cyclone V SoC or Arria V SoC design hang on boot or fail SDRAM calibration? - Why does my Cyclone V SoC or Arria V SoC design hang on boot or fail SDRAM calibration? Description Due to a problem, Cyclone® V SoC and Arria® V SoC devices may encounter the following issues for configurations with clock select (CSEL) pins set to values of 01, 10 or 11: The HPS hangs during the BootROM stage and is unable to proceed to the Preloader stage. HPS SDRAM calibration fails during the Preloader process. Resolution A patch for the Quartus® II software / SoC EDS versions 13.1 and 14.0 is available to work around this problem, follow the instructions below. Download and install the patch from the appropriate link below SoC EDS version 14.0 Download patch 0.01soc for SoC EDS version 14.0 for Windows (.exe) Download patch 0.01soc for SoC EDS version 14.0 for Linux(.run) Download the Readme for patch 0.01soc for SoC EDS version 14.0 (.txt) SoC EDS version 13.1 Download patch 0.03soc for SoC EDS version 13.1 for Windows (.exe) Download patch 0.03soc for SoC EDS version 13.1 for Linux(.run) Download the Readme for patch 0.03soc for SoC EDS version 13.1 (.txt) Notes: - Install the patch to <ACDS install path>/altera/<version>/ directory. - This patch uses the upper 4 Kbytes of the HPS on-chip RAM (OCRAM). Hence, your software that runs after Preloader must not modify the upper 4 Kbytes of the OCRAM. Connect the CSEL pins [1:0] to pull-down to ground resistors (4.7 kohm to 10 kohm) on the board, CSEL=00. In this CSEL mode the BootROM does not perform PLL configuration and the PLLs are in by-pass state upon power-up or cold reset. Regenerate the Preloader image Launch embedded command shell On Windows systems, run the batch file: <SoCEDS installation Folder>\embedded\Embedded_Command_Shell.bat On Linux systems, run the shell script: <SoCEDS installation Folder>\embedded\embedded_command_shell.sh In the command shell, change directory to <your_design_path>/software/spl_bsp Type make clean-all Note: This command removes the Preloader binary image and the uboot-socfpga folder which contains all Preloader source files. If you modified or added files into this folder previously,you should back-up those files and re-apply them after using this patch. Type make Note: Re-making the Preloader invokes extracting the Preloader source files from SoC EDS installation directory which contains the fix to this issue. Related Articles Can I disable the HPS warm reset handling code in Preloader? Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V FPGAs and SoCs', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V FPGAs and SoCs', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']