A CDR locked signal might not be stable when using serial loopback mode when simulating a Custom PHY IP for Stratix V - A CDR locked signal might not be stable when using serial loopback mode when simulating a Custom PHY IP for Stratix V
Description When you simulate a Custom PHY IP, a CDR locked signal might not be stable when using serial loopback mode. Resolution Disable serial loopback mode and use an external serial loopback in the testbench.
Custom Fields values:
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Troubleshooting
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True
['Simulation']
['FPGA Dev Tools Quartus II Software']
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10.0.1
['Stratix® V FPGAs']
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['novalue'] - 2021-08-25
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