SDRAM ECC Disabled in Preloader - SDRAM ECC Disabled in Preloader Description Qsys cannot generate a DDR interface in the HPS component with ECC enabled. If you try to specify such an interface, the result is an interface with no ECC. Depending on the interface width specified, the resulting interface width is as follows: Specified width Resulting width 24 16 40 32 Resolution Upgrade to the Altera Complete Design Suite v13.0 SP1 or later. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0.1 13.0 ['Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']