Why does my ALTDQ_DQS2 IP fail to fit? - Why does my ALTDQ_DQS2 IP fail to fit? Description This error may be seen in the Intel® Quartus® Prime Standard Edition Software on a design containing the ALTDQ_DQS2 IP. This error occurs when the read_write_data_io signal feeds back towards the core logic: Error (170143): Final fitting attempt was unsuccessful Info (170138): Failed to route the following signal(s) Info (170139): Signal "<hierachy_name>|altdq_dqs2_<device_family>:<hierachy_name>|input_path_gen[*].read_fifo_out[*]" Resolution To avoid this error, remove the read_write_data_io signal feeding back towards the core. This feedback to core connection is not allowed. Custom Fields values: ['novalue'] Troubleshooting FB: 382284; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 15.1.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']