Which ARM SoC addresses report the status of the physical FPGA-to-HPS Interrupts (f2h_irq0 and f2h_irq1 signals)? - Which ARM SoC addresses report the status of the physical FPGA-to-HPS Interrupts (f2h_irq0 and f2h_irq1 signals)? Description In the Altera SoC Hard Processor System (HPS), the raw status of the physical f2h_irq0 and f2h_irq1 interrupt signals can be read directly from the ARM® Generic Interrupt Controller (GIC) ICSPISRn registers (starting at ARM address 0xFFDE_DD04). The mapping is the following: FPGA-to-HPS irq bits 0 through 23 (f2h_irq0[23:0]) can be read from 0xFFDE_DD08 bits [31:8] FPGA-to-HPS irq bits 24 through 31 (f2h_irq0[31:24]) can be read from 0xFFDE_DD0C bits [7:0] FPGA-to-HPS irq bits 32 through 55 (f2h_irq1[23:0]) can be read from 0xFFDE_DD0C bits [31:8] FPGA-to-HPS irq bits 56 through 63 (f2h_irq1[31:24]) can be read from 0xFFDE_DD10 bits [7:0] Resolution For more information about the Generic Interrupt Controller (GIC), including setting, clearing, and masking interrupts, please refer to the Interrupt Controller chapter of the Cortex-A9 MPCoreTechnical Reference Manual, available on the ARM info center website. This information is scheduled to be included in a future release of the Cyclone® V Device Handbook Volume 3: Hard Processor System TRM. Custom Fields values: ['novalue'] Troubleshooting 2205864071 False ['Interrupt'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 13.1 ['Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']