Cyclone 10 GX EMIF Design Example: I/O assignment errors - Cyclone 10 GX EMIF Design Example: I/O assignment errors Hello, I'm following the Cyclone 10 GX EMIF IP Design Example User Guide in the below web page. 1. Design Example Quick Start Guide for External Memory Interfaces... (intel.com) The EMIF project was created accordingly. However, I met compilation errors as below. Please help me to solve the problem. The full compilation log and the archived project are attached. Thanks. [Error Message] Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Critical Warning (12677): No exact pin location assignment(s) for 653 pins of 653 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report Info (12785): Fitter finished merging On-chip termination (OCT) logic blocks Info (12786): Removing unused on-chip termination logic block "emif_c10_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_logic_inst" from the netlist Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Error (179000): Design requires 658 user-specified I/O pins -- too many to fit in the 284 user I/O pin locations available in the selected device Info (179001): Current design requires 658 user-specified I/O pins -- 658 normal user-specified I/O pins and 0 programming pins that have been constrained to use dual-purpose I/O pin locations Info (179002): Targeted device has 284 I/O pin locations available for user I/O -- 240 general-purpose I/O pins and 44 dual-purpose I/O pins Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action. Error (16297): An error has occurred while trying to initialize the plan stage. Error: Quartus Prime Fitter was unsuccessful. 3 errors, 2 warnings Error: Peak virtual memory: 6458 megabytes Error: Processing ended: Fri Apr 14 15:19:00 2023 Error: Elapsed time: 00:00:11 Replies: Re: Cyclone 10 GX EMIF Design Example: I/O assignment errors Hi Jeff, I am glad that you are successfully running full compilation. Yes the example design project directory should always generated in qii folder. All the related files are included in this folder. Regards, Adzim Replies: Re: Cyclone 10 GX EMIF Design Example: I/O assignment errors Hi Adzim, The compilation errors were found from "example_design\emif_example.qpf". When I opened the project "example_design\emif_c10_0_example_design\qii\ed_synth.qpf", the full compilation is working. Thank you so much. then, the below compilation step also indicates the qpf file under the qii folder? 1.8. Compiling and Programming the Intel® Cyclone® 10 GX EMIF Design... Regards, Jeff Replies: Re: Cyclone 10 GX EMIF Design Example: I/O assignment errors Hi Jeff, No, you should not choose "Project Template". I am thinking that you are not opened the generated example design. If you are referring to Figure 3 in Section 1.3, there is a path to where the generated example design is created. Usually, the project design is located in emif_0_example_design/qii/ed_synth.qpf Can you check the design in this path? Regards, Adzim Replies: Re: Cyclone 10 GX EMIF Design Example: I/O assignment errors Hi Adzim, Thank you for the answer. When I create the project, the type was empty project as the user guide. Do you mean I had to choose "Project template" instead of "Empty project"? I applied a DDR3 preset (DDR3-1600K CL11 Component 1CS 4Gb (256Mb x16)) with the platform designer as you suggested. My board has two 256Mb x16 DDR3 ICs. So, the DQ width was changed from 16 to 32 at the "Memory" tab in EMIF FPGA IP. "Generate Example Design" and "Generate HDL" were done again with the updated IP. However, I still see the similar compilation errors. Do you have some other suggestions for this? Regards, Jeff Replies: Re: Cyclone 10 GX EMIF Design Example: I/O assignment errors Hi Jeff, I have checked the design in the attachment. The design only has an EMIF IP and the top level is EMIF IP. This does not look like a complete example design generated by Quartus. Please follow the instruction from below link to generate an example design: https://www.intel.com/content/www/us/en/docs/programmable/683096/21-1-19-1-0/generating-the-synthesizable-emif-design.html Regards, Adzim