Why does the DisplayPort Intel® FPGA IP fail to output video when Vtotal of Main Stream Attribute (MSA) field is greater than 13-bit width? - Why does the DisplayPort Intel® FPGA IP fail to output video when Vtotal of Main Stream Attribute (MSA) field is greater than 13-bit width? Description Due to a problem in version 14.0 and later of the Intel® Quartus® Prime software, the DisplayPort Intel® FPGA IP Pixel Clock Recovery Interface Hsync and Vsync signals stick low when the condition below is met: Video resolution with Vtotal Main Stream Attribute (MSA) field exceeding 13-bit width or 8191 in decimal. Resolution This problem is fixed starting from the Intel® Quartus® Prime Pro Edition version 20.1 Software onwards. Custom Fields values: ['novalue'] Troubleshooting 1507691362 True ['DisplayPort IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] 20.1 14.0 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']