[Agilex 5] Global Clock assignment ignored for PLL output clock with high fanout - [Agilex 5] Global Clock assignment ignored for PLL output clock with high fanout Device: Agilex 5 Issue Description: The Timing Analysis report indicates that a specific PLL output clock has a fanout of 21343(see screenshot below). Does this high fanout on non-global routing imply that the clock failed to be promoted to the Global Clock Network? Suspecting this was the issue, I configured the "Global Signal" assignment to "On" in the Assignment Editor and recompiled the design. However, this setting appears to be ineffective，the fanout still 21343. 【set_instance_assignment -name GLOBAL_SIGNAL ON -to u0|clock_subsystem|iopll|iopll_1|tennm_ph2_iopll~O_OUT_CLK0】 Could you please advise if this needs to be addressed and how to successfully enforce the Global Clock assignment? Thanks. Replies: Re: [Agilex 5] Global Clock assignment ignored for PLL output clock with high fanout I got it，thank you Replies: Re: [Agilex 5] Global Clock assignment ignored for PLL output clock with high fanout I think they're same signal and had been pushed to global clock network. If you turn off global signal, the signal is not showed in Fitter's 'Global & Other Fast Signals' summary right? For clock, it's normal and healthy to still have high fanout even though had been pushed to global clock network (clock usually having high fanout). The global clock network will have low skew for those clock high fanout. The only problem is the high fanout clock but using regional routing, that'll causes skew issue. Replies: Re: [Agilex 5] Global Clock assignment ignored for PLL output clock with high fanout The picture is from the Fitter's 'Global & Other Fast Signals' summary. I believe this entry corresponds to the manual constraint I applied in the Assignment Editor. Could you please confirm if this is effectively the same signal as the one reported with a high fanout of 21,343 in the Timing Analyzer? Please advise. Thanks Replies: Re: [Agilex 5] Global Clock assignment ignored for PLL output clock with high fanout No, you should be checking the Global signals report in the compilation report in the Fitter folder I believe since this is a resource placement issue. A clock naturally has high fanout to drive everything but the global signals report indicates if the clock is using a global clock resource or being routing on standard routing wires.